Design of Phase locked loop in 180nm Technology using LT SPICE an opensoure EDA Tool. The first task started with the design of LC Voltage Controlled Oscilator.

Tools Used: LT SPICE | CADENCE |

Design of software model of Neural Network for Handwritten Digit Recognition system using Python. Hardware realization of the neural network using Verilog HDL, validating behavioral, Post synthesis & Post Implementation Simulations and then ANN is implemented on FPGA.

Tools Used: Xilinx Vivado, VS Code | FPGA Board: NEXYS A7 | Languages: Verilog HDL & Python

Utilized Gm/Id methodology to design and simulate a Two-Stage Operational Amplifier in the 180 nm technology for the specifications: Gain >1000, Gain Bandwidth Product (GBW) > 1GHz, and Phase Margin of 50.

Tools Used: LT Spice, Analog Designer Toolbox (ADT), Electric Binary.

The project covers the entire workflow of designing a FIR filter using MAC Multiplier and accumulator unit and followed by its implementtaion on to the FPGA Board, It includes the various submodules such as Multiplier, adder, RAM, ROM, register, and a Finite state machine to handle the signals like reset, load, write etc, This was successfully implememnted onto the F[GA.

Tools Used: Xilinx Vivado

The project covers the entire workflow from schematic design to GDSII generation, including pre-layout and post-layout simulations, delay calculations, RC parasitics extraction, and validation through DRC and LVS checks. The goal was to successfully implement the CMOS inverter design and perform a detailed comparison between pre-layout and post-layout simulation results.

Tools Used: Cadence Virtuoso

Explored MOSFET models for TSMC180nm, Analyzed strong 0/1 and weak 1/0 logic configurations through simulation. Designed CMOS Inverter, and analyzed its voltage transfer characteristics and key design parameters like VOH, VOL, VIH, VIL, and the switching threshold, with its layout using Electric Binary.

Tools Used: LT Spice, Electric Binary.